Wiring structure having a slit dummy

ABSTRACT

A wiring structure includes wiring embedded in an insulating layer. A plurality of slit dummies each of that spaced each other are formed in the wiring. The wiring has a first portion that has a width wider than a reference width, and has a second portion that has a width shallower than the reference width. A distance of each slit dummy is less than a width of the reference width. The slit dummies are not formed in the second portion of the wiring.

CROSS REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority under 35 U.S.C. §119 toJapanese Patent Application No. 2002-218878, filed Jul. 26, 2002, whichis herein incorporated by reference in their entirety for all purposes.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a wiring structure that has aplurality of slit dummies in a wiring.

[0004] 2. Description of the Related Art

[0005] Recently, copper is used as a wiring material to reduce theresistance of the wiring. The wiring with copper is typically fabricatedby a damascene process.

[0006] The conventional damascene process is shown in FIG. 10.

[0007] A silicon nitride film 204 is formed on a semiconductor substrate202 and a silicon oxide film 206 is formed on the silicon nitride film204 as shown in FIG. 10(A). Grooves 208 a and 208 b are formed in thesilicon oxide film 206 as shown in FIG. 10(B). Then, a copper layer isformed on the silicon oxide layer 206 including the groove as shown inFIG. 10(C). Since the copper layer is formed, the groove is embedded bythe copper layer. The copper layer on the insulating layer is removed byCMP (Chemical Mechanical Polishing) process as shown in FIG. 10(D). Thatis the copper layer is only remained in the grooves, and the remainingcopper layer is used as the wiring. Because copper has a high diffusionrate in some dielectrics, particularly silicon dioxide, some form ofbarrier layer between the insulating layer and copper layer is required.Various barrier materials have been proposed including refractory metalssuch as titanium (Ti), tantalum (Ta).

[0008] The damascene process has a problem that a thickness of thewiring is reduced during the CMP process.

[0009] As shown in FIG. 10(D), a concave portion called dishing isformed in the surface of the wiring. The FIG. 10(D) shows across-section at the width direction of the wiring. A depth D of aportion that is deepest at the dishing is increased, while the width ofthe wiring is increased.

[0010]FIG. 2 is a plot of an experimental data that shows a relationshipbetween the width of the wiring W and a variation of a sheet resistanceAR. In FIG. 2, a horizontal axis is the width of the wiring W μm and avertical axis is the variation of the sheet resistance ΔR %, while aheight of the wiring is 500 nm. According to the plot, the ΔR is 5 or 6%when the W is 2 μm, the ΔR is 20% when the W is 10 μm and the ΔR is 25%or more when the W is 20 μm. That is, while the width of the wiring isincreased, a difference between an actual resistance of the wiring and aresistance in design is increased.

[0011] In order to solve above problem, (1) a reference width is definedand (2) when a width of the wiring exceed the reference width, slitdummies are used.

[0012] The slit dummies are formed in the wiring to prevent the dishing.The slit dummies are used a different material from the wiring. The slitdummies are fabricated at the step of forming the grooves as shown inFIG. 10(B). During the grooves are formed in the silicon oxide film 206by etching the silicon oxide film 206, the slit dummies are also formedin the silicon oxide film 206 by etching. That is, the slit dummies aremade from the material to the silicon oxide film 206.

[0013]FIG. 11 is a schematic diagram of a conventional wiring structurewith slit dummies.

[0014] The copper wiring 222 is formed in the silicon oxide film 216 anda bottom of the copper wiring 222 is formed on a silicon nitride film218. Slit dummies 214 are formed in the copper wiring. Heights of theslit dummies 214 are equal to a height of the copper wiring 222.However, there is no clear standard in a length Dw and a length Dd ofthe slit dummy. Therefore, since too many slit dummies are formed in thewiring, a total width of the wiring is increased.

[0015] Accordingly, in an object of the present invention, a wiringstructure for arranging slit dummies efficiently is provided.

SUMMARY OF THE INVENTION

[0016] According to one aspect of the present invention, there isprovided a wiring structure that includes a wiring embedded in aninsulating layer. A plurality of slit dummies each of that spaced eachother are formed in the wiring. The wiring has a first portion that hasa width wider than a reference width, and has a second portion that hasa width shallower than the reference width. A distance of each slitdummy is less than a width of the reference width. The slit dummies arenot formed in the second portion of the wiring.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a schematic diagram showing an arrangement of the slitdummy of the first preferred embodiment.

[0018]FIG. 2 is a plot showing a relationship between the width of thewiring and the variation of the sheet resistance.

[0019]FIG. 3 is a cross-sectional view of the wiring with dishing.

[0020]FIG. 4 is a plot showing a relationship between the width of thewiring and the variation of the sheet resistance, and a relation shipbetween the width of the wiring and the depth of the dishing.

[0021]FIG. 5 is a plot showing a relationship between the space of theslit dummies and area ratio of the slit dummies.

[0022]FIG. 6 is a schematic diagram showing the parameter of arrangementof the slit dummies.

[0023]FIG. 7 is a plot showing a relationship between the width of thewiring and the area ratio of the slit dummies.

[0024]FIG. 8 is a schematic diagram showing the arrangement of the slitdummies in the second preferred embodiment.

[0025]FIG. 9 is a schematic diagram showing the third preferredembodiment.

[0026]FIG. 10 is a schematic diagram showing the conventional wiringprocess steps using a damascene process.

[0027]FIG. 11 is a schematic diagram showing the wiring structure thatis inserted the slit dummies.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] A wiring structure according to preferred embodiments of thepresent invention will be explained hereinafter with reference tofigures. In order to simplify explanation, like elements are given likeor corresponding reference numerals through this specification andfigures. Dual explanations of the same elements are avoided.

First Preferred Embodiment

[0029]FIG. 3 is a cross-sectional view at a width direction of a wiringthat is formed a dishing. As shown in FIG. 3, a isosceles triangle thatincludes a base that is passing through starting points of a dishing andan apex that is deepest point of the dishing is defined. Since a form ofa dishing showing in FIG. 3 approximates lines A1 and A2, a variation ofa sheet resistance ΔR, a width of the wiring, a height of the wiring anda depth of the dishing are satisfied a following approximate expression(1).

ΔR≈HW/(HW−WD/2)·1

[0030]FIG. 4 is a plot showing a relationship between the width of thewiring W and the variation of the sh WD/2)

[0031] ∴D=2HΔR/(ΔR+1)   (1)

[0032] A unit of the height of the wiring H and the depth of the dishingD is nm, and a unit of the width of the wiring W is μm.

[0033] The depth of the dishing D while the wiring has a height of 500nm is calculated from the approximate expression (1) and the variationof the sheet resistance ΔR, and a relationship between a width of thewiring W and the depth of the dishing in the height of the wiring is 500nm. A horizontal axis shows a naturalized logarithm and a vertical axisshows the variation of the sheet resistance ΔR with a unit % and thedepth of the dishing D with a unit nm.

[0034] As shown in FIG. 4, since a relationship between the naturalizedlogarithm value of the width of the wiring W and depth of the dishing Dshows a line shape, following approximate expression (2) is formed.

D≈701 nW   (2)

[0035] A unit of the depth of the dishing D is nm, and a unit of thewidth of the wiring W is μm.

[0036] Generally, a variation of the resistance is controlled in a rangeof 3 to 10%. In the first preferred embodiment, a maximum variation ofthe resistance is defined a value of 5%. That is, a reference width Wmaxthat the slit dummies are not necessary is calculated from theapproximate expressions (1) and (2).

701n(Wmax)=2H*0.05/1.05

∴Wmax=Exp(H/735)   (3)

[0037] A unit of the reference width Wmax is μm and a unit of the heightof the wiring H is nm.

[0038] While the width of the wiring W exceeds the reference width Wmax,the slit dummies are inserted in the wiring. While the width of the W isnarrower than the reference width Wmax, the slit dummies are notnecessary.

[0039] For example, the height of the wiring H is 300 nm, the referencewidth Wmax is calculated as follows.

Wmax(H=300 nm)=Exp(300/735)=1.5 μm

[0040] Therefore, the maximum width of the wiring is 1.5 μm. While thewidth of the wiring exceeds 1.5 μm, the slit dummies are used.

[0041] It is desired that minimum numbers of the slit dummies arearranged in the wiring evenly. In this embodiment, the same material ofthe silicon oxide film 102 forms the slit dummies.

[0042]FIG. 6(A) shows an arrangement of the slit dummies 106 a through106 d. All of the wiring area is included in a distance R, which definedby half of the Wmax, from a side of the slit dummy.

[0043] A shape of the slit dummy is square Wmin on a side. The Wmin is aminimum size of fabrication. The side of the slit dummy is arranged inparallel to the long direction of the wiring.

[0044] First, the slit dummies 106 a and 106 b are arranged on acenterline of the long direction of the wiring. The centerline isarranged at middle of the width of the wiring. Each of the slit dummies106 a and 106 b have a distance L from each other.

[0045] Middle points of each side of the slit dummies 106 a and 106 bare defined as M1 and M2. Two circles each of that has a radius R andthe central pints M1 and M2 have intersections B1 and B2. A point C1 isarranged at a distance R from the pint B1 in the width direction of thewiring. A point C2 is arranged at a distance R from the point B2 in thewidth direction of the wiring. The slit dummies 106 c and 106 d arearranged on a line passing through the points C1 and C2. The points C1and C2 are arranged at middle point of facing sides of the slit dummies106 c and 106 d.

[0046]FIG. 6(B) through FIG. 6(D) shows a variation of the arrangementof the slit dummies.

[0047] If the points C1 and C2 are arranged in the silicon oxide film102, or arranged on line of the boundary between the wiring 104 and thesilicon oxide film 102, the slit dummies 106 a and 106 b are arranged inthe wiring 104 without the slit dummies 106 c and 106 d, as shown inFIG. 6(B).

[0048] If the points C1 and C2 are arranged across the silicon oxidefilm 102 and the wiring 104, a distance Dh between the edge of thewiring 104 and the points C1 or C2 are size of width direction of theslit dummies 106 c and 106 d, as shown in FIG. 6(C).

[0049] As shown in FIG. 6(D), if the slit dummies 106 c and 106 dcontacts to the edge of the wiring 104, the square Wmin on the side ofslit dummies 106 a, 106 b, 106 c and 106 d are arranged in according toabove rules.

[0050]FIG. 5 is a plot that shows a relationship between a distance ofthe slit dummies L and an area ratio Q of the dummies in the wiring,when the reference width Wmax is 2 μm and the width of the slit dummyWmin is 0.2 μm. The distance of the slit dummies L is defined by αR, theα is a factor for exchanging to the R. The distance between the slitdummies L is shown in horizontal axis with a unit μm, and the area ratioQ of the dummies in the wiring is shown in vertical axis with a unit %.

[0051] The area ratio Q of the dummies in the wiring is a value that thetotal area of the slit dummies Sd per unit area Sp is divided by theunit area Sp.

[0052] Since the width of the slit dummies are vanishingly, the unitarea Sp is calculated the space L by the width W. Therefore, the arearatio of the slit dummies in the unit area is an area ratio of the slitdummies in the total area of the wiring.

[0053] A case of the width is 3.6 μm shows as follows. The total area ofthe slit dummies Sd is varied in accordance with the distance betweenthe slit dummies L. The total area of the slit dummies Sd in the unitarea Sp is calculated as follows.

[0054] (a) 0.2<L≦1.2: A number of slit dummies are one. Sd=Wmin*Wmin

[0055] (b) 1.2<L<1.6: A number of slit dummies are three.Sd=Wmin*Wmin+Wmin*Dh*2

[0056] (c) 1.6≦L≦2.0: A number of slit dummies are three. Sd=Wmin*Wmin*3

[0057] The area ratio of the slit dummies Q is calculated by dividingthe total area of the slit dummies Sd by the unit area Sp.

Q=Sd/Sp

[0058] The area ratio of the slit dummies Q plotted in the vertical axisshows an average of the area ratio of the slit dummies of a pluralitypoint of the width. The area ratio of the slit dummies is averaged ofthe wiring width of 2.1 μm to 4.2 μm at every 0.1 μm.

[0059] In the relationship between the a and the Q shown in FIG. 5, whenthe distance between the slit dummies L is {square root}3R, the arearatio of the slit dummies becomes minimum. That is, the area ratio ofthe slit dummies Q becomes 1.3%.

[0060] While the length in the length direction of the wiring of theslit dummy is Dd, the length Dd is shown as Dd=(S−L) based on the pitchof the slit dummies S and the space of the slit dummies. That is, thepitch S satisfied Dd<S≦2R+Dd. Therefore, the expression (S−L)<S≦2R+Dd isformed.

[0061] The pitch of the slit dummies S is usable as equal to the space Lof the slit dummies, when the arrangement of the slit dummies isdefined. That is, the following description about the arrangement of theslit dummies is described by using the pitch of the slit dummies S.

[0062] A rule of arrangement of the slit dummies in the wiring shows asfollows.

[0063] Step 1: The reference width Wmax is calculated from the varietyof the sheet resistance.

[0064] Step 2: The pitch S of the slit dummies is defined by theexpression S={square root}3 Wmax/2.

[0065] Step 3: The rule of arrangement of the slit dummies.

[0066] These steps are described in FIG. 1(A) to FIG. 1(C).

[0067] The slit dummies are arranged along the long direction of thewiring with the pitch S, when the width W is wider than the referencewidth Wmax.

[0068] When the pitch S is {square root}3 Wmax/2, a distance between theadjacent slit dummies lines Dp is 3 Wmax/4 by the rules defined in FIG.6.

[0069] The arrangement of the slit dummies 106 is defined by followingrules in the width W.

[0070] (a) W≦Wmax: The slit dummy is not used as shown in FIG. 1(A).

[0071] (b) Wmax<W≦3 Wmax/2: The slit dummies 106 are arranged. Each ofthe slit dummies is arranged on the middle line O with an even pitch S(S={square root}3 Wmax/2), as shown in FIG. 1(B).

[0072] (c) 3 Wmax/2<W≦9 Wmax/4: Each of the slit dummies is arranged onlines O1 and O2. The lines O1 and O2 are located at equal spaces (3Wmax/8) from the middle line O of the wiring. The slit dummies arrangedon the line O1 is half pitch staggered to the slit dummies arranged onthe line O2, as shown in FIG. 1(C).

[0073] (d) 9 Wmax/4<W≦3 Wmax: The slit dummies are arranged on threelines O, O3 and O4. The line O is a middle line of the wiring, and thelines O3 and O4 are located at equal spaces (3 Wmax/4) from the middleline O. The slit dummies arranged on one line is half pitch staggered tothe slit dummies arranged on the next line, as shown in FIG. 1(D).

[0074] When four or more slit dummy lines are needed, the slit dummiesare arranged as follows. In the following rules, the numbers of the slitdummy lines n are four or more.

[0075] When the even number of the slit dummy line is used, two slitdummy lines are arranged at the distance 3 Wmax/8 from the middle line Oas shown in FIG. 1(C), and the other slit dummy lines are arranged atthe distance 3 Wmax/4 from the next slit dummy line. The slit dummiesarranged on one line is half pitch staggered to the slit dummiesarranged on the next line.

[0076] When the odd number of the slit dummy line is used, one slitdummy line is arranged on the middle line O as shown in FIG. 1(D), andthe other slit dummy lines are arranged at the distance 3 Wmax/4 fromthe next slit dummy line. The slit dummies arranged on one line is halfpitch staggered to the slit dummies arranged on the next line.

[0077] In order to the steps described above, the rule of arrangement ofthe slit dummy lines is defined.

[0078] According to the first preferred embodiment, the slit dummies arearranged appropriately. That is, a reducing of the area of the wiringcausing to introduce the slit dummies in the wiring is reduced. Further,since the slit dummies are used, the dishing causing the CMP process isreduced. As a result, the variation of the resistance of the wiring isreduced.

Second Preferred Embodiment

[0079]FIG. 7 is a plot showing a relationship between the area ratio Q %of the slit dummies and the width W μm of the wiring, when the slitdummies are arranged in the rule defined in the first preferredembodiment. In the rule of the first preferred embodiment, since thearea ratio Q of the slit dummies is not constant to the width W of thewiring, an actual resistance of the wiring is different from a designedresistance of the wiring.

[0080] In order to the plot of FIG. 7, the area ratio of the slitdummies Q in the wiring has a small value that 0.7% to 1.6%. When thewidth of the wiring W is wide for example the width is 100 μm or more,the slit dummies are polished during the CMP process. As a result,controlling the dishing in the wiring is difficult.

[0081] In the second preferred embodiment, the area ratio of the slitdummies Q is 15% to 30%.

[0082] In the basic arrangement of the slit dummies 106, the slitdummies are arranged on the middle line O of the width of the wiring. Anincreased area of the wiring is defined as a wiring area that is removeda width of 3 Wmax/8 from each side of the wiring.

[0083] Then, the arrangement of the slit dummies is defined, so as tothe slit dummies are included in the increased area of the wiring with aratio of 20%.

[0084] Detailed rules are shown in following steps.

[0085] (a) W≦Wmax: The slit dummy is not used as shown in FIG. 8(A).When the wiring includes a plurality of wiring lines, each of the wiringlines are arranged at an area ratio of 80%, for preventing the dishing.

[0086] (b) Wmax<W≦3 Wmax/4+Wmin (FIG. 8(B)): A length of the slit dummyin the long direction of the wiring is Dd, and a length of the slitdummy in the width direction of the wiring is Dw. The length Dd is0.2*{square root}3 Wmax/2. Since the slit dummies are formed in theincreased area of the wiring 108 with the area ratio of the wiring in aunit area of the increased area of 20%, the length Dw is smaller thanthe Wmin. Since the slit dummies area arranged on the middle line in thelong direction of the wiring, it is not fabricated desired size. Twoslit dummies having a width of hafl of Dw and a length of 0.2*{squareroot}3 Wmax/2 are arranged at edge of the wiring. When the Wmin issmaller than ¼ Wmax, the slit dummy is not used.

[0087] In the following description of the arrangement of the slitdummies, the length Dw is the minimum size of fabrication Wmin. Thepitch S is {square root}3 Wmax/2.

[0088] (c) W=3 Wmax/4+Wmin: The slit dummy having a length Dd of(0.2*{square root}3 Wmax)/2 is arranged on the middle line of thewiring, as shown in FIG. 8(c).

[0089] (d) 3 Wmax/4+Wmin<W≦3 Wmax/4+4 Wmin: The slit dummy having alength Dd of ({square root}3 Wmax*(W−3 Wmax/4)*0.2)/Wmin is arranged onthe middle line of the wiring, as shown in FIG. 8(d).

[0090] (e) W=3 Wmax/4+4 Wmin: In this condition, the length Dd of theslit dummy is 0.8*{square root}3 Wmax/2, and the pitch achieves 80%.When the length Dd of the slit dummy is longer than the 0.8*{squareroot}3 Wmax/2, the wiring may be divided by the slit dummy. Therefore,when the length Dd of the slit dummy exceeds the length of 0.8*{squareroot}3 Wmax/2, the slit dummy is divided in two parts and the slitdummies are arranged on two lines. The slit dummies that is arranged onone line is half pitch staggered to the slit dummies arranged on theother line, as shown in FIG. 8(E).

[0091] If the slit dummies are arranged on number of line at 2^(k)(k isan integer of k≧2), the slit dummies are arranged as follows.

[0092] When the width of the wiring W is achieves every W=3Wmax/4+2^((k+1)) Wmin (k is natural number), the slit dummies arrangedone line is divided by two lines. Therefore, the slit dummies arearranged in the increased area at area ratio of 20%.

[0093] According to the second preferred embodiment, the slit dummiesare arranged in the wiring at area ratio of approximately 20%. As aresult, the dishing is reduced and the actual resistance of the wiringis near the designed resistance of the wiring.

Third Preferred Embodiment

[0094] In the third preferred embodiment, when the wiring has a widththat is wider than the reference width Wmax, the wiring is formed bycombination of units of the slit dummy pattern. The unit of the slitdummy pattern includes a wiring area and a slit dummy in the wiringarea, and the area ratio of the slit dummy is 20%.

[0095] In the third preferred embodiment, the unit of the slit dummypattern has the width of the wiring W. A design freedom is lost, but astep for designing the slit dummies is reduced.

[0096]FIG. 9(A) shows the unit slit dummy pattern 112. A width of theunit slit dummy pattern 112 is 3 Wmin. The unit of the slit dummypattern has a slit dummy 114 that has a width of Wmin and an area ratioof 20%. The units of the slit dummy pattern arranged in line define aline pattern. When the width of the wiring W is 12 Wmin, four linepatterns are arranged in contact with each other. The unit of the slitdummy pattern that is arranged on one line is half pitch staggered tothe unit of the slit dummy pattern that is arranged on next line, asshown in FIG. 9(B).

[0097] If the width of the wiring is n times of the width of the unit ofthe slit dummy pattern, n lines of the unit of the slit dummy patternare arranged in contact with each other. The unit of the slit dummypattern that is arranged on one line is half pitch staggered to the unitof the slit dummy pattern that is arranged on next line, as shown inFIG. 9(B).

[0098] In the end in long direction of the wiring, when the unit slitdummy pattern is crossed the boundary of the unit of the slit dummypattern, the slit dummy is not inserted.

[0099] In the third preferred embodiment, the copper wiring has slitdummies that are evenly arranged is fabricated, as shown in FIG. 9(C).

[0100] According to the third preferred embodiment, it is easy to designthe layout of the wiring that includes the slit dummies.

[0101] While the preferred form of the present invention has beendescribed, it is to be understood that modifications will be apparent tothose skilled in the art without departing from the spirit of theinvention. The scope of the invention is to be determined solely by thefollowing claims.

What is claimed is:
 1. A wiring structure comprising: an insulatinglayer including a grove; a plurality of slit dummies each of which isspaced from each other in the grove; and a wiring which is formed in thegrove, the wiring has a first portion which has a width longer than areference width, and has a second portion which has a width narrowerthan the reference width; wherein distance between slit dummies are lessthan a width of the reference width; wherein the slit dummies are notformed in the second portion of the wiring.
 2. A wiring structureaccording to claim 1, wherein the reference width is defined asExp(H/735), wherein H is thickness of the wiring.
 3. A wiring structureaccording to claim 2, wherein the slit dummies are arranged in a lineand arranged along a direction in which the wiring extends.
 4. A wiringstructure according to claim 3, wherein the slit dummies are arrangedspaced equally.
 5. A wiring structure according to claim 2, wherein theslit dummies are arranged in plural lines, wherein the slit dummies inthe lines are arranged in staggered form.
 6. A wiring structureaccording to claim 5, wherein the slit dummies are arranged spacedequally.
 7. A wiring structure according to claim 6, wherein the slitdummies arranged in one of the lines are arranged adjacent to the edgeof the wiring.
 8. A wiring structure according to claim 6, wherein adistance between the lines is approximately {square root}3 half ofreference width.
 9. A wiring structure according to claim 2, whereindistance between slit dummies are approximately 85% of the width of thereference width.
 10. A wiring structure according to claim 1, wherein amaterial of the slit dummies are the same as that of the insulatinglayer.